Design Services

Architecture/system definition

Gate estimation and partitioning

Standards expertise

• I2C, SPI, I2C, CAN, PCI, SDIO, WiFi, BT, BTLE, SNAP, HDMI, various telecom protocols

FPGA/CPLD/discrete design using ORCAD and Allegro Embedded microcontrollers

• Freescale Kinetis, Vybrid, i.MX, Atmel, TI, and other ARM architectures
• Intel 80C32/52 family

Optimal placement for high density and speed performance, low EMI Technologies

• CMOS, BiCMOS, Bipolar, ECL, analog rigid, rigid flex, and flex substrates
• Controlled impedance, blind, buried and stacked vias/HDI design rules for minimal area and low EMI
• FR-4,FR-370HR, CEM3, Kapton flex

Prototyping and verification

• Fast-turn PCB fabrication and assembly coordinated
• Full lab facilities for verification
• Environmental testing
• EMI/ESD/EMS compliance testing support

Foundry selection based on

• Technology - deep sub-micron CMOS, Bipolar, Gate array, standard cell
• Price
• Time-to-market
• Libraries, IP/cores, custom cells

RTL/schematic design

• Using Verilog, VHDL, ORCAD, Allegro, ...
• Clock tree synthesis/Clock trunk balancing

Design Verification

• Pre-layout simulation, SDF back annotation and post-layout simulation
• Static timing analysis

Synthesis

• Using Synopsis
• Synthesisable RTL code developed for an optimal solution

Test verification

• Design-For-Test options BIST, Scan and JTAG
• High fault coverage test suites developed

FPGA / CPLD prototyping using Altera, Xilinx, Lattice Design reuse

• Re-targeting or leveraging previous designs and IP/core
• IP/core designs integrated and tested

Floorplanning

• For speed and/or size constraints
• IO definition for optimal ASIC and PCB routing
• Critical paths specified

Custom cells defined and verified